Conventional memories use an external bus of restricted width to move a data page in small portions at a time between corresponding locations in different page-frames in a memory. Such conventional memories are currently used in microcomputers, minicomputers and large computers.
Conventional computer systems have long had a processing unit (PRU) having registers and logic circuits external to the main memory, with the PRU receiving and manipulating the bits in a byte or word(s) accessed in the memory. The PRU functions included adding, shifting, etc. After any manipulation, the PRU often transfers the data back to the memory, which may be to a different memory location than the location from which the data was originally accessed. Data is commonly shifted by the PRU externally of the memory to align the data across block boundaries within the memory. Data could also pass unchanged through the PRU during the process of moving data from one memory location to another memory location.
An external bus was required by such prior computer systems to transfer each unit of data (byte or words) between the memory and the PRU before putting the manipulated data back into the memory, often to a different chip than the chip from which the data was fetched.
Any PRU shift function was not capable of directly changing the location of data within the memory. At most, memory address values (received by the PRU on the external memory bus) could be manipulated by the PRU before being sent to the memory on the bus for use as conventional memory addresses.
The external busing resulted in slow memory operation because of the limited external bus width which limited the number of bits that could be handled simultaneously in parallel. This bus width constraint is sometimes referred to as a bandwidth limitation on the memory operation, because it slowed the computer operation. For these and other reasons, prior computer memories were incapable of operating in the manner of the subject invention.
Input/output pins connect memory chips to the external bus. The I/O pin number is limited on each memory chip, thereby limiting the number of bits that can be simultaneously transferred to the PRU for instruction-controlled operations in a computer system. Conventional computers execute all intra-memory data move operations (including page moves) by transferring the data to the external bus and through the PRU. For example, a common operation in the IBM S/370 computer is the moving of one or more pages (4096 bytes or 32,768 bits per page) to different page-frame location(s) in the memory using a Move Character Long instruction, for which a PRU has used a sequence of bus-limited move operations external to memory to move each page of data, so that a page could not be moved in one parallel operation. Each page move operation is broken into a number of serial submove operations, each submove operation transferring a bus-width limited number of bits, which is not a restriction on page moves with the subject invention.
Conventional computer memories are currently made of random access memory (RAM) semiconductor chips. Conventional memories are easily extendable by adding chips to the old memory chips. The old chips were retained when extending the memories.
Such conventional memories have addressability-control switches which must have their addressability settings changed when chips are added for increasing the size and addressability of the memory.
U.S. Pat. No. 4,476,524 to D. T. Brown et al entitled "Page Storage Control Method" describes the use of an external bus for moving page units in bus-width limited groups of bits between an expanded storage (L4) and a main storage (L3).
An article by T. C. Lo (one of the inventors of the subject invention) entitled "Integrated L3/L4 Concept" is in the IBM TDB on page 98, volume 31, Number 2, dated July 1988. This article (which does not disclose the claimed invention in the subject application) discloses a memory structure which included both L3 and L4 memories to obtain non-bus page transfers between L3 and L4 memories. But the disclosed memory structure could not be changed and maintain an internal L3/L4 memory page transfer, since an external bus would be required for internal page transfers if chips were added to the memory structure (unlike the subject invention).
U.S. Pat. No. 3,654,622 deals with a memory system comprised of a 2-dimensional array of shift registers and the concurrent selection of two adjacent shift registers, to cross word boundaries and avoid the loss of time entailed in switching to the next adjacent shift register.
U.S. Pat. No. 3,740,723 to Beausoleil et al entitled "Integral Hierarchical Binary Storage Element" discloses memory chips using 2-dimensional addressing which may have a shift registers at the intersections of the 2-dimensional address selections. Also, shift registers are disclosed for outputting data to a buffer store. A page-move operation entirely internal to a chip cannot be done in this patent similar to the manner it is done by the subject invention.
An article in the IBM TDB January 1977 at page 3071 by F. J. Aichelmann, Jr. and N. M. DiPilato entitled "Hierarchy Memory for Improved Microprocessor Performance" discloses a page store chip hierarchy.
An article in the IBM TDB June 1981 at page 485 by F. J. Aichelmann, Jr. entitled "Paging From Multiple Bit Array Without Distributed Buffering" discloses a full page buffer in a controller.
An article in the IBM TDB May 1984 at page 6473 by R. C. Tong entitled "Memory Transfer at Arbitrary Byte Boundaries" disclosed the use of one or two shift registers external to the chips comprising a memory, for which the shift registers performed an PRU function of reordering the bit sequence in a byte location in the memory, by transferring the byte on a bus from the memory to the register, reordering the bits in the byte, and writing the reordered byte back into the memory.
U.S. Pat. No. 4,577,293 to Matick et al discloses a distributed cache located on the same chips as the main system memory. Data is transferred to a second port from the memory by first being moved on the same chips in a single cycle from the cache to the second port, which sends the bits to a CPU. Bits from the CPU are received at the second port and put into the cache in one or more cycles, and the cache data is moved into the memory on the same chips in a single cycle.
U.S. Pat. No. 4,491,910 to Caudel et al entitled "Microcomputer Having Data Shift Within Memory", and U.S. Pat. No. 4,586,131 to Caudel et al entitled "Microcomputer Having Data Move Circuits For Within-Memory shift of Data Words" have the same specification. They disclose the subject matter of the following claim limitation: "shift means moving an entire data word in the memory from one location to another location having an adjacent address". The disclosure does not appear to have the capability of moving a data word to any location in the memory using the shift means.
U.S. Pat. No. 4,641,276 to Dunki-Jacobs disclosed a data communication method and means for transferring data in parallel to a source register, serially shifting the data from the source register to a destination register, and then transferring the data in parallel to another functional unit.
U.S. Pat. No. 4,667,313 to Pinkham et al uses a shift register to access a row of bits obtained from a memory bus to be serially accessed at a tapped position in the shift register.
U.S. Pat. No. 4,725,945 to Kronstadt et al entitled "Distributed Cache in Dynamic RAMs" discloses a cache memory chip arrangement using fast-registers within the chips. No page move operations appear to be disclosed.
U.S. Pat. No. 4,731,758 to Lam et al discloses separate arrays on the same chip connected through a transfer gate.
None of the above cited prior art suggests the claimed subject matter in the subject application.
Prior memories generally required the use of an external bus in order to move a page between internal memory page locations. The prior memories could accommodate 4 kilobyte (KB) page sizes, but such memories were not generally organized as page-type memories, even when they were commonly used to move pages of data. Prior computer systems generally allowed for a range of memory sizes from a minimum to a maximum in the organization of their random access memories without any special consideration for the page operations in the memories. Extension of the prior memories from a minimum to a maximum size allowed the addition of new chips to the old chips in the memory. The prior memories may be made of a DRAM chips having a single or multiple types of internal chip organization.